This invention relates generally to the field of hard-disk drives. More specifically, this invention relates to an improved circuit architecture and method to generate write precompensation delay in a high-density, partial-response magnetic recording system.
A hard-disk drive (xe2x80x9cHDDxe2x80x9d) in a computer system contains tracks onto which information is stored magnetically. This information is stored as a series of magnetic polarity transitions (i.e., ones and zeros), and is stored on the disk drive as the drive rotates. The magnetized areas on the disk act like individual magnets. As the density of information stored on the disk increases, the poles of the areas begin to interact causing the magnetized areas to shift, and inter-symbol interference increases. This, in turn, causes errors when the data is read.
xe2x80x9cWrite precompensationxe2x80x9d (WPC) is used to solve this problem. Precompensation (or xe2x80x9cprecompensation delayxe2x80x9d) is necessary to compensate the non-linearity of transition edges arising in magnetic media recording. WPC shifts data bits forward when they are being written to the disk in order to compensate for shifting that occurs when a data bit is written next to it. When the next data bit is written, the interaction between the poles shifts the data bit into its proper position.
In a HDD partial-response system, one method of implementing WPC is to use the master clock (which is used to write the data to the disk) to generate a ramp waveform and then to compare the ramp waveform to threshold voltages to generate delayed triggering pulses for the data transition edges. As shown in FIG. 1, ramp waveform 120 has the same frequency as master clock 110. For one half of each period of ramp waveform 120, the waveform is at a high level. For the other half of each period of ramp waveform 120, the waveform linearly decreases toward a low level. When the ramp voltage becomes less than a threshold voltage, a clock pulse is generated whose rising edge is time-delayed from the start of the ramp. For a high threshold voltage 130, the delayed clock pulses 155 are wider; for a low threshold voltage 140, the delayed clock pulses 165 are narrower, and their rising edges begin later.
Precompensation delay is determined by the delay between the rising edges of the delayed clock pulses. By convention, high threshold delayed clock signal 150 is considered the reference delay clock, generating 0% precompensation delay. The precompensation delay amount generated by low threshold voltage delayed clock signal 160 is the percentage of the full master clock period between its rising edge and that of the reference delay clock. In the example shown in FIG. 1, approximately 30% of the master clock period lies in interval 170 between the rising edges of the two delayed clocks. Thus, the system in FIG. 1 can provide 30% precompensation delay.
The type of system in FIG. 1 is limited in the amount of delay it can provide, relative to the master clock period. Because the ramp waveform is high for half the master clock period, the theoretical maximum delay, assuming all voltages and switching times are exact, is limited to less than half the master clock period. For a practical system, some margin must be included and the threshold voltages must be set well away from the high and low levels of the ramp waveform. Therefore, as in the system of FIG. 1, the maximum delay is limited to around 30% of the master clock period. As recording density and clock rate increases, the switching time between adjacent transitions is reduced, and the amount of precompensation required increases as a percentage of the switching time. As required precompensation increases to over 30% and more, these conventional WPC circuits are not able to supply enough precompensation delay.
Therefore, a need has arisen for an improved write precompensation signal generation circuit and method which allow precompensation of more than 50% of the master clock period.
In accordance with the present invention, a circuit for generating a write precompensation signal having precompensation delay includes a precoder, a delayed clock pulse selector, a delayed clock pulse generator, and a non-return-to-zero (NRZ) modulator. A master clock signal and serialized data operating at the master clock rate are inputs to the precoder which generates a precoded data signal operating at the master clock rate. The delayed clock pulse selector generates clock pulse selection signals based on the precoded data. The delayed clock pulse generator generates at least two delayed clock signals, selects either none or one of the delayed clock signals according to the clock pulse selection signals, and generates a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of the selected delayed clock signal. The NRZ modulator generates the precompensation signal from the RZ signal, and the precompensation signal has a maximum precompensation delay of at least 50% of the master clock time period.
Preferably, the precoder includes a D-flip flop whose clock input operates at the master clock rate and an XOR gate which has the serialized input data as its first input and the output of the D-flip flop as its second input. The output of the XOR gate is provided to the data input of the D-flip flop, and the output of the D-flip flop is the precoded data signal.
Preferably, when four delayed clock signals are generated, the clock pulse selection signals are based on the current precoded data and the prior two precoded data bits. If the current precoded data bit equals zero, the delayed clock pulse generator selects no delayed clock signal. If the current precoded data bit equals one, the delayed clock pulse generator selects one delayed clock signal based on the values of the previous two precoded data bits, as follows: (1) the first delayed clock signal is selected when the previous two precoded data bits both equal zero; (2) the second delayed clock signal is selected when the previous two precoded data bits equal a zero and a one, respectively; (3) the third delayed clock signal is selected when the previous two precoded data bits equal a one and a zero, respectively; and (4) the fourth delayed clock signal is selected when the previous two precoded data bits both equal one.
Preferably, the precompensation circuit also includes a ramp waveform and threshold voltage generator to generate at least one ramp waveform and at least two threshold voltages. The delayed clock pulse generator compares the ramp waveform to the threshold voltages to generate the delayed clock signals. More specifically, there is also a current generator that generates a current that is proportional to the master clock frequency and provides the proportional current to the ramp waveform and threshold voltage generator. Because of the proportional current, the peak-to-peak voltage of the ramp waveform is maintained constant regardless of the master clock rate.
A preferred embodiment of the present invention also includes a time-interleaver which time-interleaves the precoded data signal into odd and even data sequences each operating at half the master clock rate. The clock pulse selection signals are then based on the time-interleaved data sequences. The delayed clock pulse generator generates at least two odd and two even delayed clock signals and generates an odd RZ signal and an even RZ signal, each of which operates at half the master clock rate. The NRZ modulator generates the RZ signal by combining the odd and even RZ signals. Preferably, the ramp waveform and threshold voltage generator generates an odd and an even waveform.
Preferably, the time-interleaver includes a D-flip flop, whose clock input operates at the master clock rate, that generates an odd clock signal and an even clock signal, each of which operates at half the master clock rate. The time-interleaver also includes a series of odd D-flip flops clocked by the odd clock signal and a series of even D-flip flops clocked by the even clock signal. The precoded data signal is provided to the odd and even series of D-flip flops which output the odd and even data sequences.
The method for generating the write precompensation signal having precompensation delay includes precoding the serialized input data operating at the master clock rate, generating at least two delayed clock signals, selecting either none or one of the delayed clock signals based on the precoded data, generating an RZ signal operating at the master clock rate, and generating the precompensation signal as an NRZ version of the RZ signal. Each time period of the RZ signal comprises either a zero if no delayed clock signal is selected or a pulse of the selected delayed clock signal. The precompensation signal has a maximum precompensation delay of at least 50% of the master clock time period.
Preferably, the preceding step provides the serialized input data bits to a first input of a two-input XOR gate, providing the output from the XOR gate to the input of a D-flip flop whose clock input operates at the master clock rate, and providing the output from the D-flip flop to the second input of the XOR gate. The output of the D-flip flop is the precoded data signal.
Preferably, the delayed clock pulse generating step generates four delayed clock signals. The delayed clock signals are selected according to the following protocol: if the current precoded data bit equals zero, no delayed clock signal is selected, and if the current precoded data bit equals one, a delayed clock signal is selected based on the values of the previous two precoded data bits, as follows: (1) a first delayed clock signal is selected when the previous two precoded data bits both equal zero; (2) a second delayed clock signal is selected when the previous two precoded data bits equal a zero and a one, respectively; (3) a third delayed clock signal is selected when the previous two preceded data bits equal a one and a zero, respectively; and (4) a fourth delayed clock signal is selected when the previous two precoded data bits both equal one.
Preferably, the delayed clock signal generation step includes generating a ramp waveform, generating a threshold voltage, providing the threshold voltage to the non-inverting input of a comparator, and providing the ramp waveform to the inverting input of the comparator. The output of the comparator is the delayed clock signal. Preferably, the ramp waveform has a constant peak-to-peak voltage regardless of the master clock rate.
A preferred embodiment of the method of the present invention also includes time-interleaving the precoded data signal into odd and even data sequences each operating at half the master clock rate and generating at least two odd and two even delayed clock signals. The RZ signal is a combination of an odd RZ signal and an even RZ signal, the odd and even RZ signals operating at half the master clock rate.
Preferably, the time-interleaving step includes generating an odd clock signal and an even clock signal each operating at half the master clock rate and providing the precoded data to an odd series of D-flip flops clocked by the odd clock signal and to an even series of D-flip flops clocked by the even clock signal.
The present invention provides various technical advantages. As used in a HDD system, one technical advantage is that a write precompensation signal is generated that provides more than 50% precompensation delay. Another technical advantage is the use of a current which is proportional to zone frequency. This current provides a fixed ramp waveform peak-to-peak amplitude regardless of zone frequency. Another technical advantage is that as HDD operating speeds increase, the present invention provides such precompensation delay robustly and minimizes inter-symbol interference.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.